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PlanAhead Deep Dive Part 2: New Project Flow

This is the second in the series of a Deep Dive into the Xilinx tool called PlanAhead.  Check out part 1 here.

So you want to be a hardware designer hu?  Cool.  Well we better get started right away!

Note: I am using Windows 7 64 bit and version 14.2 of the tools for this how-to.  If you need help getting your tools up and running, check out this post.

First, launch PlanAhead:

If you are not on a 64 bit machine, you are going to want to launch the 32 bit version of PlanAhead, not the 64 bit version.

When you launch the tool you will notice that a dos-box opens and prints some information about licensing.  Once the license has been obtained, you will see that the GUI is launched.  It looks like this:

We have a series of options here, so let's go through them.

Getting Started

Create New Project:
Well this is pretty self describing - this is where we would go to create a new project.  If you have existing code blocks, IP, or constraint files that you want to use in a new project, this is still where you are going to go to do that.

Open Project:
If you have already started a project, or are opening a design that someone else has given you this is where you want to go.  You will be prompted to navigate to a .ppr or .xise project file.  The .ppr file is the native PlanAhead project file.  the .xise project file is a ISE project file that PlanAhead will help you convert over if you so wish.

Open Recent Project:
This is nice if you are in the middle of a design, and have been working on it using this machine, then you can just click this option and select your project from the drop down menu.

Open Example Project:
This is really useful if you are just getting started and you don't want to fiddle with writing code.  There are a few example projects available to you that are simple, CPU based, and/or core-generator based.


Release Notes Guide:
This option is going to launch your web browser and bring you to the release notes for the version of PlanAhead you are using.  These can be particularly interesting when migrating your project between versions of the tools.

User Guide:
Everything, in my opinion, should have a users guide.  Luckly Xilinx feels the same way :D.  Clicking this option will launch your web browser to the PlanAhead users guide.  This can be nice when you have a question about something very specific that a Google Search might not return anything on, or I have not touched on here.

Methodology Guides:
This option also launches your web browser to the Xilinx website to their "Product Support & Documentation" page.  There is a plethora of information here - use the search function to refine your search.

PlanAhead Tutorials:
This option will launched your web browser and bring you to the Tutorials page on the Xilinx website.  At the time of this blog post there was only 1 tutorial, and that was using ChipScope in a design.

Ok, now that we know what all of our options are - let's create a new design.  This will always be the launch point of how you will start a new design.  Click "Create New Project".  You will be presented with the Create a New PlanAhead Project wizard.  Click Next to get past the intro page.

The first page is "Project Name".  Name your project something intelligent and descriptive enough to come back to later easily (ie. don't call it project_1 ...).  Note:  Don't put spaces in your project name, nor should you have spaces in your directory names.  Also try and stay away from long directory names (greater than 256 characters).

Name your project and hit Next.  I named mine "simple_design", and I placed it in c:/Xilinx/Projects

On the next page, Project Type, you are presented with 5 different types of projects.  Let's go through them one by one.

RTL Project:
In this context RTL stands for Real Time Logic.  This option will allow you to add and create source code files in VHDL and/or Verilog.  This is my traditional flow as I find I often need to add glue logic to designs that I can do easily with some VHDL.  If you plan on writing HDL, this is the project type you should pick.

Post-synthesis Project:
This allows us to create a project that does not require synthesis to happen.  We can add files that have already been synthesized.  This can be useful if you are using a third-party synthesis tool.

I/O Planning project:
This can be nice if you are the hardware designer and just want to get an idea of what IO configuration is going to work best for you.  This option allows you to just configure what pins will do what in your design.

Import ISE Place & Route results:
As mentioned in Part 1 of this series, as well as in previous posts, ISE was the previous recommended tool for all design work for Xilinx FPGA's and CPLD's.  Today, we live in the PlanAhead world - but that doesn't mean that you may not have ISE projects.  This option allows you to import already routed designs into PlanAhead from ISE.

Imported Project:
This option is for project conversion.  There are three different project types supported: Synplify is a third party tool that performs synthesis on HDL.  XST is the engine that performs most of the steps described in part 1 of this series.  ISE is the previous IDE (integrated development environment) used to target Xilinx tools.

I am going to assume that the majority of projects are going to be using the RTL flow - so I am going to continue down that path.

On the next page is our option to "Add Sources".  We can Add Files, Add Directories, or Create File.

Add Files:
Here we can add files that already exist on the disk.  This is useful if you are bringing in code from previous projects (code re-usability is a good thing).

Add Directories:
Here we can add entire directory of source files.  PlanAhead will attempt to import any files in the directory and interpret them appropriately.

Create File ...:
This option allows you to create a new file to be added to your project.  If you click Create File ... you will get a small popup asking for the name of the file to be created, what language it is going to be, and where it will be saved to:

Here I have chosen VHDL, my language of choice, but if you prefer Verilog, choose that.  Select a file name that makes sense.  I prefer to name my top module "top.vhd", but this will create a bitstream file called top.bit - not terribly descriptive.  Note: don't put spaces in your file names!

After you click OK, you will return back to the Add Sources screen.  If you are done, click Next.

The next screen is the "Add Existing IP (optional)" screen.  Here we have the ability to add existing IP that we have created, is Xilinx provided, or purchased from a third-party company.  If you click the "Add Files..." button you will see a File Open Dialog box will show up, which is looking for a .xco, or .xci file.  These files are pre-synthesized net lists - often encrypted for distribution.  Once you are done here, click Next.

This next page is called "Add Constraints (optional)".  I briefly talked about constraints in Part 1 of this blog post.  It is an in-depth enough topic that I would like to devote an entire blog post to it.  If you have constraint files you would like to add, here is where you would do it.  Note you can add multiple constraint files and perform different runs against them to generate different results in both the Synthesis and Implementation sections of the Flow Navigator.

Once you are done adding your constraint files, click Next.  This next page is the "Default Part" screen - it is daunting at first, but don't worry, it's pretty straight forward.

Xilinx has been around for a long time, and thus they have a great deal of awesome FPGA and CPLD offerings.  With that being said, you need to know which device you are going to use to move past this screen.

In the traditional flow of a project, usually the designer at least has an idea of what kind of performance is needed, and thus knows what family of FPGA they are going to be in.  For this exercise I am going to target the Spartan-6 LX4, since it is very small and my synthesis and implement times will be short.  Here is what my screen looks like:

I've selected the XC6SLX4-2TQG144C device from the list.  Once you have selected this, or another device you would like to target, click Next.

The final screen is a summary page.  Note that you may have some exclamation points there if you did not add certain file types - this is just an informative output, it does not mean anything is wrong with your configuration.  When you are happy with the information provided, click Finish.

The Create Project progress bar window will show up briefly, and then the PlanAhead GUI will display.  If you added a new file to your project, like I did, a small wizard will automatically launch.  It will look like this:

Here we have the ability to define our signals that will come in and out of our new file (or module).  I have named mine 'top' so that is why the Entity name is top.  Note: You can change the entity name to something different than this, but then you will have an entity name and file name that do not match, which can lead to nightmarish debugging - protip: don't do that.

I am going to define some ports here.  If you know what ports you are going to be using, their direction, type, and size you can do the same.  If you do not know what any ports are going to be, I highly recommend just adding one of them.  If you add at least one port then the tool will create the template correctly for you.  Here is what my ports look like:

Here we have three ports defined:

clk - this port will be the clock in which all of our flip flops within our design will trigger off of.  Xilinx FPGA's are synchronous by design - this means you should always have a clock.

reset - we will use a reset signal to change all of our LED's back to all zero's.  This is a nice feature to have so we can reset a canned demo.  This also gives us the ability to bring the FPGA back to a known state at any time.

leds - this is our output to the world: 8 LED's.  We will simply be making our LED's count up from 0 to 255, and then roll over.

Once you understand what we are looking at here, click the OK button to create the file.

Ok, once the PlanAhead GUI is back to usable (after the wizard closes) find the Project Manger part of the window, and specifically the Sources section within it:

Within the sources section, you will see Design Sources and Constraints.  You should see your added files (in this case I have just the top.vhd file) within the Design Sources folder.  If you added constraints then you will see then within the Constraints folder - I did not add any, so there are none to display.

Double click on your top module - this will cause the editor to open the file for editing as shown above.  This is where you begin to edit your file and add the code you want.

That concludes part 2 of the PlanAhead Deep Dive.  Next we will write some code, and run it through synthesis.


Hi~ I've been watching your website for a few weeks. Congratulation for your new space on Zynq!!
Is RTL stands for Real Time Logic? I learn it was Register-Transfer Level. You can check on this wiki.

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