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PlanAhead Deep Dive Part 1: Flow Navigator

This is the first of a series of posts that hope to better explain the PlanAhead software and some of it's features.  I have broken it up into different parts so it flows a bit nicer.  I will link the other posts here once I complete them.

I've put together a post or two so far that use one of the Xilinx software tools called PlanAhead.  This tool is the replacement for a software tool that has been with Xilinx for quite some time called ISE.  Those who have used Xilinx before the 13.x and 14.x tool chain will be very familiar with ISE.

PlanAhead has actually be hiding out within the install of the ISE tool chain for a few versions now.  PlanAhead has been called when doing certain tasks such as floor planning (actually placing equations within logic cells), as well as some IO constrain functions.

As of the 14.x tools Xilinx has decided to push for PlanAhead to be the primary development tool for all future projects.  So, with that being said, we should probably learn how to use it!

First let's take a look at the basic idea of how PlanAhead works.  It is written primarily in Java and calls externally to a series of other tools to perform various parts of the conversion from HDL to a bitstream.  These external tools can be grouped into a few primary categories  and are found on the left side of the PlanAhead tool within the Flow Navigator.

Let's take these one at a time so we can better understand our tool.

Project Navigator:
The project navigator catigory allows for configuration and control of your project.  Here we see there are 4 different options.  Each of these have different functions that I will describe below:

Project Settings:
The project settings option brings up a nice little window that describes how the tool will interpret your project.  Settings like your target device, perfered language, simulator settings can be modifed here.

Note: All of the "xyz Settings" options within the Flow Navigator (where zyz is either Project, Synthesis, Implementation, or Bitstream) will actually open the same window, just on different tabs.

Add Sources:
This is exactly what it hits at being.  Use this option to add additional sources to your project.  These sources can be a wide variety of different types based on what project type you are working with.  This launches a small wizard that helps you create new sources or import existing ones.

IP Catalog:
This is where things get really awesome.  This is a small wizard that allows you access to different Intellectual Property (IP) blocks of code that Xilinx has written, tested, validated, and compiled to a netlist for you.  They are optimized and validated to work the way they are documented to.

The IP Catalog opens as a new tab within PlanAhead (which is nice so you can keep it open for later use).

Here you can see I have navigated to the Math Functions -> Divider -> Divider Generator.  This will then launch a small wizard that will allow you to configure the IP Block for your specific use.  Take a second to browse through these - there are a lot of them and they are all very useful.

Run Behavioral Simulation:
As you continue to become more and more proficient and familiar with FPGA design and the Xilinx tools you will quickly notice that creating a bitstream every time you change something is really, really, REALLY, inconvenient.  Xilinx was nice enough to give us a way to test our code without having to go through all of the steps.

There is a mixed language HDL simulation tool within the Xilinx Tool Chain called iSIM.  I am not going to touch on this here as it is a pretty awesome tool that has a lot to offer.  A separate blog post on that later.

In short, this option allows you to run a simulation of your code against a specified testbench that will spit out useful information about how your code is behaving.

RTL Analysis:
In this context RTL stands for Real Time Logic.  TRL Analysis is a set of tools that can be used to analyize your code after you have turned it into usable logic from your source files.  I am going to skip past this as well as it is rather complicated and we don't yet have a design.  I will come back to this another time.  If you have a need to know more about this - post and I'll see what I can do for a how-to.

Synthesis:
Ok, now were getting into the good stuff.  Think of Synthesis as a conversion step.  This step takes your HDL code and converts it into a 'binary' file called a netlist.  This netlist is just that, a list of different nets (networks) that describe the logic equations you wrote in your HDL files.  This netlist is necessary for the next step that is going to take that netlist and map it to Xilinx specific hardware primitives  then place and route the netlist and primitives within the FPGA fabric.

Synthesis Settings:
This launches the settings window for Synthesis.  Here you will see a series of options that you can configure your Synthesis engine, XST for the 14.2 tools, as well as define a Strategy.  Strategies are new for PlanAhead, and did not exist (within the tools explicitly at least) within ISE.

Strategies are pretty slick.  They allow you to define a few sets of configuration options that will produce a certain result, and then run the code against all of them to see which one gets you the result you wanted.  PlanAhead streamlines the "tweak and run and tweak" method that is often found when doing FPGA design.

The other thing you can configure here are your constraints.  Constraints are one of the most delicate, however one of the most important parts to ensuring a fast, large design works well.  I will most definitely do a separate blog post on this and link to it once it is done.  But for now, keep this default.

Run Synthesis:
Well this isn't too cryptic - it performs the actual synthesis of your source files.  Depending on how large your project is, and how much code you have written and the libraries it pulls from, this can be fairly quick, or quite lengthy.

Open Synthesized Design:
Within this option are additional options.  Here is a brief description of each:

    Edit Timing Constraints: These are the constraints I was talking about before that we will not be touching on here.

    Report Cock Interaction: This option helps you see how the clocks in your design are being used by the logic within your design.

    Report DRC: This option performs a Design Rule Check (DRC) against a set of predefined rules on what is allowed and what is not within Xilinx hardware.  Note: you can create a netlist that will not work in hardware.

    Report Noise: This option has the tools perform their best estimation on the amount of noise IO pins will experience  and will allow.

    Report Utilization: Just like in software with respect to available code space, there are a finite number of logic cells and primitives within the FPGA.  This option shows you the current usage of your code of these logic cells and primitives.  This can be very useful when you are trying to optimize code size.

    Schematic:  This is a nice way to visualize your project.  This option will turn your 'compiled' netlist into a visual, browse-able schematic.  This is especially nice for documentation and sanity checking when you are presented with an excessive number of warnings during Synthesis.

Implementation:
Implementation used to be separated into three different steps within ISE: Translate, Map, and Place and Route.  In PlanAhead we have a single point to perform all three of these 'steps'.  Implementation is taking the netlist from the Synthesis step and actually turning it into a configuration that is usable on the specific Xilinx FPGA you are using.  Each family of FPGA's and CPLD's have different things inside of them that the tools can utilize to make your design better.  The implementation step takes the netlist of equations and tuns them into Xilinx specific equations.

Implementation Settings:
This launches the settings window for Implementation.  Here you will see a great deal of options that you can tweak to get your design to go faster, and be smaller.  You will also see that there are strategies just like in the Synthesis options menu.  You can run your code against different sets of options to generate different results.

Run Implementation:
This actually performs the Implementation step.  This calls a number of XST tools that work together to generate the output of the Implementation step.

Open Implemented Design:
Here there are number of options for report generation and constraint modification.  Let's take a look at each one:

    Edit Timing Constraints: One of the ways to get a design to meet timing and run the way you want it to within your FPGA fabric is to apply timing constraints on specific portions of your design.  This allows the tools to use different methods and metrics to determine the best way to turn your netlist into a usable configuration by the FPGA.  This option opens a new tab that allows you to modify these constraints   The 'art' of timing constraints is something I will touch on in a different blog post as it can become rather involved.

    Run TRCE: TRCE is a static timing analysis tool which can be rather involved to use.  I am not going to touch on it much here.  This allows you better granularity than the basic reports into the timing of your FPGA design.  When running TRCE it will open in a new tab at the bottom of the PlanAhead window and will display timing information for various nets within your design.

    Report Clock Interactions: This option will open a tool that will describe how your equations interact with the various clocks within your design.  This can be useful to try and pin down a pesky bottleneck that is preventing your design from meeting timing.  Note: if you only have one clock this option is not terrible useful (in my opinion).

    Report DRC: In this context DRC stands for Design Rule Check.  When you run this option you will be prompted to select the parts of the design in which you want the DRC to run on.  Pick which parts you would like to perform DRC on and click OK.  This doesn't take too long to run, and the results will show up on the bottom of the PlanAhead window in a new tab.  This can be nice so you can see all of your warnings/errors in one location.

    Report Noise:  This option has the tools perform their best estimation on the amount of noise IO pins will experience  and will allow.  This is the same general feel of the same option under Synthesis, however it is being performed after Implementation so the results will be more accurate.

    Report Utilization:  As mentioned previously, FPGA's only have so much 'stuff' within them.  They have a set number of primitives (DSP blocks, Memory, Clock Buffers, etc), as well as logic cells.  This report will tell you how much of each you are using.  This can be nice when making estimates to whether you are in a too big or not big enough device.

    XPower Analyzer:  The XPower Analyzer is a really power tool that gives a pretty darn accurate estimation of what the power consumption of your design will be.  This is REALLY helpful when designing power suppliers for a new design.  It also will help you determine if you need active or passive cooling for your design.  This tool is really nice, and I would like to do a separate post on it, so I will not dive into it here.

    FPGA Editor:  The FPGA Editor is a tool that has existed in the Xilinx tools for quite some time now.  It actually allows you to move equations around within the FPGA fabric as you desire.  This can be very useful if you aren't meeting timing, but you think you know why and it is a small issue (sometimes on really large designs, or designs that use close to all of the FPGA's resources, the tools have a hard time and mis-route signals in not the most efficient way.).

    Run Timing Simulation:  This will launch the iSIM simulator with your top design as the UUT (Unit Under Test).  You will need to set this up to run it correctly from PlanAhead.  I am not going to touch on this here as I will be posting an iSIM how-to.

Program and Debug:
Ok, now that you have your design implemented we need to create the actual bit-stream that is going to be loaded into the FPGA via JTAG or by a Flash device on power-on.  We have just four options within this section.

Bitstream Settings:
As before, this launches the settings for the bitstream creation.  There isn't much to configure here as we really have our design created at this point.

Generate Bitstream:
Actually create the bitstream.  This calls a program called bitgen which actually takes the output from Implementation and turns it into a usable stream of configuration bits that the FPGA uses to configure itself.

Launch ChipScope Analyzer:
Think of ChipScope as a logic analyzer that you can load into your FPGA design and look at any signal within it in real-time while you are running your design - crazy powerful.  This option doesn't do much unless you are planning on using ChipScope and have it within your design.  So I am going to skip over it for now.

Edit:  There is a nice tutorial of using ChipScope in the PlanAhead tutorals section on the Xilinx website:

    http://www.xilinx.com/support/documentation/dt_planahead_planahead14-2_tutorials.htm

Launch iMPACT:
As mentioned in a few other posts iMPACT is the tool that actually loads the bitstream into the FPGA via JTAG, or uses the FPGA to load that bitstream into a piece of Flash in your design (or on the development board you are using).  Take a look here for a brief post on how to use iMPACT.

Well, there you have it ... the Flow Navigator described in detail for PlanAhead.  PlanAhead is a really slick tool, and has some really great features.  Tune back in soon for additional parts to this little series.

Comments

Hey
I generated the system.bit unfortunately when I want export hardware for sdk I can't chekck the box include bitstream I don't understand. I use the ise 14.4. Do you have ideas of the problem ?
Cordially.

If the checkbox to include the bitstream is not available, it does usually mean that the bitstream wasn't successfully created. Did you double-check to see if you received any errors during the build?
Bryan